It is common for a high speed data converter to employ a data weighted averaging (DWA) algorithm as a solution to achieve dynamic element matching (DEM). FIG. 1 illustrates a comparison of the operation of a data converter 102 that does not employ DWA and a data converter 104 that does employ DWA. A data word 110 is received and processed by the converter circuit to actuate the output elements (OE) of a digital to analog converter (DAC). In this example, the DAC includes seven output elements.
For the data converter 102, the data word 110 is decoded by a thermometer decoder 120 to generate a control signal 122 whose data bits selectively actuate the output elements 124. If the data word has a value of 3 (binary format <0,1,1>), the thermometer decoder 120 decodes that word to generate a seven bit control signal 122 having a value of <1,1,1,0,0,0,0> which causes the first three output elements 124 from the left side to be actuated. Shaded boxes indicate an output element that is activated, while the non-shaded boxes indicate an output element that is deactivated. If the next data word has a value of 1 (binary format <0,0,1>), the thermometer decoder 120 decodes that word to generate a seven bit control signal 122 having a value of <1,0,0,0,0,0,0> which causes the only the first output element 124 from the left side to be actuated. The operation for the next data words with values of 5 and 4 are also shown.
It will be noted that this data converter 102 disproportionately actuates the output elements 124. In other words, the output elements on the left side of the DAC will be actuated more frequently than the output elements on the right side of the DAC. This will not be a problem in an ideal scenario when all output elements 124 of the DAC are identical. However, in practical designs, such a mismatch exists and manifests at the output as an increase in the noise floor of the output signal. This negatively impacts the performance of the DAC and results in a reduced signal to noise ratio. The DWA algorithm ensures that the mismatch across the unary output elements 124 is high-passed and pushed out beyond the band of interest. This is akin to first order noise shaping.
For the data converter 104, the data word 110 is processed by a dynamic element matching (DEM) circuit 130 implementing a data weighted averaging (DWA) algorithm to generate a control signal 132 whose data bits selectively actuate the output elements (OE) 134. If the data word has a value of 3 (binary format <0,1,1>), the DEM 130 decodes that word to generate a seven bit control signal 122 having a value of <1,1,1,0,0,0,0> which causes the first three output elements 124 from the left side to be actuated. Shaded boxes indicate an output element that is activated, while the non-shaded boxes indicate an output element that is deactivated. At this point, there is no difference in the operation of the data converter 104 compared to the data converter 102. If the next data word has a value of 1 (binary format <0,0,1>), the DEM 130 decodes that word to generate a seven bit control signal 122 having a value of <0,0,0,1,0,0,0> which causes the next sequential one (i.e., only the fourth) output element 124 to be actuated. If the next data word has a value of 5 (binary format <1,0,1>), the DEM 130 decodes that word to generate a seven bit control signal 122 having a value of <1,1,0,0,1,1,1> which causes the next sequential five (i.e., the last three and the first two) output elements 124 to be actuated (in this case necessitating a wraparound from the right side to the left side). The operation for the next data word with a value 4 is also shown which causes actuation of the next sequential four output elements. It will be noted that this data converter 104 over time will relatively equally actuate all of the output elements 134.
Notwithstanding the mismatch that exists with respect to the output elements of the digital to analog converter, the data weighted averaging algorithm causes actuation to be spread relatively equally over all of the output elements. The noise due to output element mismatch is shaped by the DWA which advantageously averages out the mismatch error in the band of interest.
Circuits to implement a high speed data converter that employ a data weighted averaging algorithm to achieve dynamic element matching are well known in the art. An example of such a circuit is show in FIG. 2 which illustrates a block diagram of a continuous time sigma-delta modulator using a time interleaved reference DWA architecture. The configuration and operation of the FIG. 2 circuit will not be discussed herein as such information may be obtained by reference to Dayanik, et al., “A 5GS/s 156 MHz BW 70 dB DR Continuous-Time Sigma-Delta Modulator with Time-Interleaved Reference Data-Weighted Averaging,” 2017 Symposium on VLI Circuits, 2017 (incorporated by reference). Concerns with this solution, and other similar solutions known in the prior art, include: operation is cumbersome due to a high conversion time which limits throughput and performance; the circuit is area and power inefficient; and the use of interleaving introduces high level of complexity. The complexity is further illustrated by the need for decoder and adder logic to perform dynamic indexing functions. Performance of the circuit is also adversely affected by the use of multiple parallel paths for interleaving.
There is accordingly a need in the art for a high speed data converter that operates with a low computational delay and is area and power efficient. The needed circuit should preferably avoid use of a complex decoder and adder circuit and avoid use of interleaved structures.